Charge pump circuits are widely used in a lot of electronic devices for obtaining voltage values higher than the supply voltage by using capacitors as charge storage elements.
A classic charge pump circuit comprises four capacitors suitably connected to four enable signals (or phases) of the charge pump circuit.
It is known that a four-phase charge pump circuit is able to operate in a range of frequencies equal to 10-50 MHz. However, such a range is insufficient for many applications, in particular for those applications where it is essential to save area since an increase in the phase frequency allows a reduction of the sizes of the pump capacitors, and thus the area occupied by the circuit as a whole.
FIG. 1 shows a known latch-type charge pump circuit.
The charge pump circuit 1 has an input terminal IN connected to a first voltage reference, in particular the supply voltage Vdd, and an output terminal OUT connected to a load, which is represented in the figure by a load capacitor CL connected in parallel with a load current generator IL between the output terminal OUT and a second voltage reference, in particular ground GND.
The charge pump circuit 1 has N charge pump stages CB1 to CBN connected in cascade between the input IN and output OUT terminals, and connected to first FX and second FN enable terminals that respectively supply first and second enable signals (or phases), which for simplicity are likewise indicated with the references FX and FN. In particular, the enable signals (or phases) FX and FN are complementary to one another.
The charge pump circuit 1 is thus a two-phase circuit, able to operate at quite high frequencies (e.g., 100 MHz and more), due to the presence of suitable latch circuits L1 to LN in each charge pump stage.
In more detail, each charge pump stage CBj comprises at least one first CUp and at least one second CDown pump capacitor connected between the first enable terminal FX and a first inner circuit node Up and between the second enable terminal FN and a second inner circuit node Down, respectively.
Each pump charge stage CBj also comprises a respective latch circuit Li including low voltage transistors connected between the first Up and second Down inner circuit nodes. In particular, each latch circuit Li comprises at least one pair of N-channel MOS transistors and at least one pair of P-channel MOS transistors, suitably connected so as to form opposite pairs of CMOS switches having control (or gate) terminals connected to the enable terminals FX and FN for the switched connection (and the relative charge sharing) of the pump capacitors CUp and CDown, respectively.
For a better understanding of the operation of the latch-type charge pump circuit 1 reference will be made to the simplified diagram of FIG. 2, in which only a first CB1 and a second CB2 charge pump stage are shown.
The charge pump stages CB1 and CB2 are placed in parallel and work with each other in phase opposition, with the enable signals (or phases) FX and FN being, at any time, complementary to one another. Thus, for example, when the first phase FN is high (for example, it has a voltage value near the supply voltage Vdd), the second phase FX is low (for example, it has a voltage value near ground GND).
In more detail, the first charge pump stage CB1 comprises a first pump capacitor CUp1 connected between the first enable terminal FX and a first inner circuit node Up1, a second pump capacitor CDown1 connected between the second enable terminal FN and a second inner circuit node Down1, and a first latch circuit L1 connected between the first Up1 and second Down1 inner circuit nodes and connected to an input terminal IN and to an intermediate circuit node INT.
In particular, the first latch circuit L1 comprises a first N-channel MOS transistor MNU1 and a second P-channel MOS transistor MPU1 having common bulk and drain terminals, being connected in series between the input terminal IN and the intermediate circuit node INT, and having their control (or gate) terminals connected to each other and to the second inner circuit node Down1 so as to form a first CMOS switch. The first latch circuit L1 also comprises, in a dual way, a third N-channel MOS transistor MND1 and a fourth P-channel MOS transistor MPD1 having common bulk and drain terminals, being connected in series between the input terminal IN and the intermediate circuit node INT, and having their control (or gate) terminals connected to each other and to the first inner circuit node Up1 so as to form a second CMOS switch.
In a similar way, the second charge pump stage CB2 comprises a third charge pump capacitor CUp2 connected between the second enable terminal FN and a third inner circuit node Up2, a fourth pump capacitor CDown2 connected between the first enable terminal FN and a fourth inner circuit node Down1, and a second latch circuit L2 connected between the third Up2 and fourth Down2 inner circuit nodes and connected to the intermediate circuit node INT and to the output terminal OUT.
In particular, the second latch circuit L2 comprises a fifth N-channel MOS transistor MNU2 and a sixth P-channel MOS transistor MPU2 having common bulk and drain terminals, being connected in series between the intermediate circuit node INT and the output terminal OUT, and having their control (or gate) terminals connected to each other and to the fourth inner circuit node Down2 so as to form a third CMOS switch. The second latch circuit L2 comprises, in a dual way, a seventh N-channel MOS transistor MND1 and an eighth P-channel MOS transistor MPD1 having common bulk and drain terminals, being connected in series between the intermediate circuit node INT and the output terminal OUT, and having their control (or gate) terminals connected to each other and to the third inner circuit node Up1 so as to form a fourth CMOS switch.
Under these conditions, the fourth transistor MPD1 of the first latch circuit L1 and the seventh transistor MND2 of the second latch circuit L2 are on and allow a charge sharing between the second and fourth pump capacitors Cdown1 and Cdown2, and thus charge sharing between the third pump capacitor Cup2 and the output terminal OUT, while the second transistor MPU1 of the first latch circuit L1 and the fifth transistor MNU2 of the second latch circuit L2 are off. In other words, these transistors act as pass-transistors for the charge sharing carried out by the charge pump circuit 1.
The voltage value VInt on the intermediate circuit node INT is maintained practically constant during the whole clock period, as shown in FIG. 3. This figure illustrates the typical pattern of voltage signals VCDown1 and VCDown2 at the inner circuit nodes Down1 and Down2 of the stages CB1 and CB2, together with the voltage signal Vint on the intermediate circuit node INT.
The widening of the operating frequency range allows a reduction of the sizes of the charge pump capacitors CUp and CDown, and thus of the area occupied.
However, the use of these same charge pump capacitors CUp and CDown for the turn-on and turn-off of the latch circuit transistors allows a significant circuit simplification to be obtained for the charge pump circuit 1, but also constitutes a limit of the latch circuits current supply, in particular when the supply voltage Vdd approaches the threshold voltage of the transistors in these latch circuits or when the charge pump circuit 1 is made to supply a higher and higher current value.
When the supply voltage Vdd decreases, the charge pump circuit 1 does not succeed in supplying a sufficient load current IL, as shown in FIG. 4. This figure shows the current-voltage characteristic [I-V] of the known charge pump circuit 1 for a supply voltage value Vdd equal to 1V. In particular, it shows how the I-V characteristic of the charge pump circuit 1 falls for output voltage Vout values higher than 4V.
For overcoming this limit, it is possible to increase the sizes of the transistors contained in the latch circuits and the charge pump capacitors CUp and CDown so as to meet the required specifications. However, this nullifies the simplicity of the charge pump circuit 1.
Moreover, it is possible to experimentally verify that it is not possible to obtain sufficient values of the load current IL for several applications, in particular in those circuits in which the supply voltage is near the threshold voltage of the transistors, also over-sizing the charge pump circuit 1.
This limit has become more and more problematic during recent years due to the trend of having lower and lower supply voltages.